A clock conditioner is typically used to generate desired output clock frequencies with low jitter and low phase noise based on an input reference clock. Typical clock conditioners generate an output clock by phase-locking the output of a voltage controlled oscillator (VCO) or a voltage controlled crystal oscillator (VCXO) to an input reference clock using a phase-locked loop (PLL). The input clock may be a clock signal generated by another component, or it may be a clock that is recovered from a received digital signal.
In order to improve system-level reliability, two or more clocks signals may be provided as inputs to a clock conditioner. One of these input clocks is selected as the PLL reference clock input. If the selected input clock fails or otherwise becomes unusable, the next available input clock may be selected and used as the new PLL reference clock input. This is commonly referred to as input clock switching. If all available input clocks fail or are otherwise unusable, the clock conditioner must still generate a reasonably accurate output clock for a certain amount of time. In this case, the clock conditioner is said to operate in holdover mode. Different systems may require a clock conditioner to operate in holdover mode for different amounts of time.
When a clock conditioner is operating in holdover mode and an input clock signal becomes available that is suitable to use as the PLL reference clock input, the clock conditioner exits holdover mode and resumes normal operations mode. This transition from holdover mode to normal operation mode must be completed as quickly and seamlessly as possible. When transitioning from holdover mode to normal operations mode, it is desirable, or required by some systems, to minimize the impact of this transition on the frequency and phase of the output clocks being generated as outputs by the clock conditioner.
One potential issue that may cause problematic disturbances during the exit-holdover transition is significant phase differences in the counter inputs to the phase detector of a PLL. In a clock conditioner, the inputs to the phase detector of the PLL are an input counter that is driven by a reference clock input and a feedback counter that is driven by a feedback clock generated as an output of the PLL. In the worst case, the phase difference in the inputs to the PLL phase detector can be as large as 180 degrees, since there is no deterministic phase relationship between the outputs to the two counters. Such large phase difference can cause significant disturbances in the operation of PLL, such as delays in the time required for the PLL to relock to the reference clock, delays in completing the exit-holdover transition, and/or transient frequency/phase errors in the output clocks.
Certain conventional clock conditioners avoid these problems caused by a significant phase difference in the inputs to the phase detector by waiting to exit holdover mode until the phase detector inputs, the input counter and the feedback counter, are phase-aligned. This conventional technique can be used to reduce transient frequency/phase errors in the output clock when exiting holdover. However, one drawback of this conventional technique is that the wait time for the phase detector inputs to align is uncertain and may be too long for certain conditions. For example, if the phase error between the input counter and feedback counter is 180 degrees and the frequency error between these signals is relatively small, the rate of change of the phase difference during the alignment of the two input signals may be very slow. In this case, it may take prohibitively long to wait for the phase alignment of the input counter and the feedback counter inputs to the phase detector. This delay in alignment of the phase detector inputs may prevent the clock conditioner from exiting holdover mode in some cases, as discussed in more detail below. Additionally, the uncertainty in the duration of this alignment delay results in the clock conditioner behaving unpredictably during the holdover transition thus may fail to meet requirements of some systems.
Accordingly there is a need for an improved clock conditioner capable of quickly and seamlessly exiting holdover mode and further capable of executing the holdover transition in a manner that minimizes problematic disturbances caused by uncertain phase differences in the inputs to the clock conditioner PLL.